1. Field of the Invention
The present invention relates to a wafer level package and a manufacturing method thereof; and, more particularly, to a WLP (Wafer Level Package) capable of improving bonding reliability between an under bump metal and a bump formed on an upper part thereof by forming a buffer pattern on a central part of the under bump metal of a metal wiring layer through a trench and a manufacturing method thereof.
2. Description of the Related Art
As electronic appliances have become gradually smaller, lighter, high speed and high capacity, the development of a semiconductor package with a new structure has been needed so that the semiconductor package corresponds to the development trend of the electronic appliances. A WLP (Wafer Level Package) has been known as a semiconductor package most suitable for miniaturization and high speed among semiconductor packages introduced so far.
The WLP is a package which is progressed and formed in a state in which a semiconductor chip is not separated from a wafer.
Hereinafter, a conventional wafer level package will be described with reference to a related drawing.
FIG. 1 is a cross-sectional view showing a conventional wafer level package.
Referring to FIG. 1, a wafer level package includes a silicon substrate 10 having a chip pad 11 and a passivation layer 12 to protect the chip pad 11.
And, an insulation layer 13 (Hereinafter, referring to as ‘a first insulation layer’) having a predetermined thickness is formed on an upper surface of the silicon substrate 10 to expose the chip pad 11 and a metal wiring layer 14 connected to the chip pad 11 and a ball pad unit 15 are formed on an upper part of the first insulation layer 13 to rearrange the chip pad 11.
Further, on the metal wiring layer 14 and the ball pad unit 15, a second insulation layer 16 is formed to cover the first insulation layer 13 and the metal wiring layer 14 and exposes a part of the ball pad unit 15.
In addition, a circular solder ball 17 is formed on the ball pad unit 15 exposed by the second insulation layer 16.
However, the conventional wafer level package manufactured in a wafer level has disadvantages of increasing resistance by causing a crack of an interface between the ball pad unit 15 and the solder ball 17 when mounting the solder ball 17 and of reducing reliability of a device by causing an open phenomenon in case of excessive resistance.
In order to improve a bonding failure of the solder ball 17, Japanese Patent No. 3975569 has been published for two ball bumps in the name of SONY CORP.
The above-mentioned “two ball bumps” are capable of regulating heat stress between a semiconductor device and a print wiring substrate and improving the intensity of a bonding portion therebetween by including a first solder ball bump composed of a high melting point solder formed on an electrode pad of the semiconductor device and a second solder ball bump which is overlapped with the first solder ball bump at least in a vertical direction with respect to the electrode pad.
However, there is a disadvantage of increasing a chip size and the number of processes by forming a multilayer solder ball.
Further, there is a disadvantage of reducing a signal transmission speed by increasing parasitic capacitance formed on a substrate, an insulation layer and a ball pad when increasing an area of the solder ball.